FPGA based Implementation of High Speed Double Precision Floating Point Multiplier with Tiling Technique using Verilog

• Published in: International journal of computer applications 2012-01, Vol.58 (21), p.17-25
• Main Authors: Ramesh, Addanki Purna, N Tilak, A V, Prasad, A M
• Format: Article
• Language: English
• Subjects: Acceptability; Clocks; Field programmable gate arrays; Floating point arithmetic; High speed; Multipliers; Signal processing; Tiling
• ISSN: 0975-8887; 0975-8887
• DOI: 10.5120/9407-3814

Floating point arithmetic is widely used in many areas, especially scientific computation and signal processing. For many signal processing, and graphics applications, it is acceptable to trade off some accuracy (in the least significant bit positions) for faster and better implementations. . Multiplication is the second basic operation of arithmetic. However, most of these modern applications need higher frequency or low latency of operations with minimal area occupancy. In this paper we describe an implementation of high speed IEEE 754 double precision floating point multiplier using tiling technique and targeted for Xilinx Virtex-6 Field Programmable Gate Array. Verilog is used to implement the design. The multiplier implemented with optimized area and high speed operation with latency of seven clock cycles, the design achieves 436. 815 MFlops which is 97% fast and this design occupies 433 slices which is 38. 6% more area compared to Xilinx floating point multiplier core. It handles the overflow, underflow cases and truncation rounding mode.