High-speed low-power multiplexer-based selector for priority policy

The native feature of priority policy, an extremely unbalanced encoder signal delay, causes inefficient throughput in synchronous clock systems. To balance all propagation paths, this study improves efficiency by integrating the multiplexer-based data selector and priority encoder. [Display omitted]...

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Bibliographic Details
Published in:Computers & electrical engineering 2013-02, Vol.39 (2), p.202-213
Main Authors: Chiu, Jih-ching, Yang, Kai-ming
Format: Article
Language:English
Subjects:
Balancing
Computer simulation
Design engineering
Logic
Multiplexing
Policies
Priorities
Selectors
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Summary:The native feature of priority policy, an extremely unbalanced encoder signal delay, causes inefficient throughput in synchronous clock systems. To balance all propagation paths, this study improves efficiency by integrating the multiplexer-based data selector and priority encoder. [Display omitted] ► The nature of priority policy causes inefficient throughput in synchronous clock systems. ► The proposed design balance propagation paths by integrating priority the encoder and data selector. ► The proposed priority scheme improves extremely unbalanced delays between the highest and lowest weight. ► The balanced propagation path technique is suitable for extending numerous requests. The nature of priority policy causes inefficient throughput in synchronous clock systems because of an unbalanced propagation path. To improve speed, the proposed priority scheme improves extremely unbalanced delays between the highest and lowest weight by integrating the multiplexer-based date selector with the priority encoder. Balanced propagation paths are analyzed based on the gate-level evaluation and demonstrated by post-layout simulation. In terms of scalability, this design is suitable for extending width and has a latency of only O(logm) for m requests. The proposed design also improves the critical path by using delayed-precharge technology for dynamic logic and transmission gate at transistor level. The simulation results show that, for 8–128 requests cases, this approach achieves balanced propagation paths from fastest to lowest path. The proposed design achieves a 4.5 speedup and a 57.2% decrease in power dissipation.
ISSN:0045-7906
1879-0755
DOI:10.1016/j.compeleceng.2012.12.002