Tamper Resistance Simulation on Algorithm Level Design

SUMMARY Recently, side‐channel attacks have become a serious problem. These attacks estimate the secret keys of cryptography circuits embedded in hardware. In particular, the most threatening side‐channel attacks are differential power analysis and correlation power analysis, which use the correlati...

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Bibliographic Details
Published in:Electrical engineering in Japan 2014-01, Vol.186 (2), p.40-51
Main Authors: Yoshikawa, Masaya, Asai, Toshiya, Shiozaki, Mitsuru, Fujino, Takeshi
Format: Article
Language:English
Subjects:
algorithm level simulation
Algorithms
cryptography circuit
side-channel attack
tamper resistance
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Summary:SUMMARY Recently, side‐channel attacks have become a serious problem. These attacks estimate the secret keys of cryptography circuits embedded in hardware. In particular, the most threatening side‐channel attacks are differential power analysis and correlation power analysis, which use the correlation between information processing and power consumption, which are related to secret keys in cryptography circuits. Therefore, new measures are required to prevent confidential information in cryptography circuits from being leaked to side‐channel information, such as power consumption. When designing preventive measures, resistance to side‐channel attacks, for instance tamper resistance, must be evaluated. This study proposes a new simulation method by which tamper resistance can be verified in the algorithm and architecture design phases. Experimental results show the validity of the proposed simulation method. © 2013 Wiley Periodicals, Inc. Electr Eng Jpn, 186(2): 40–51, 2014; Published online in Wiley Online Library (wileyonlinelibrary.com). DOI 10.1002/eej.22342
ISSN:0424-7760
1520-6416
DOI:10.1002/eej.22342