A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-V rm TH Read-Port, and Offset Cell VDD Biasing Techniques

In previous SRAM designs, reducing minimum operating voltage (VDDmin) inevitably resulted in devices with a large cell area (A). This work proposes an L-shaped 7T cell (L7T) and read-bitline (RBL) swing expansion scheme (RBL-EXPD) to minimize A ast VDDmin for low-voltage applications. This L7T featu...

Full description

Saved in:
Bibliographic Details
Published in:IEEE journal of solid-state circuits 2013-10, Vol.48 (10), p.2558-2569
Main Authors: Chang, Meng-Fan, Chen, Ming-Pin, Chen, Lai-Fu, Yang, Shu-Meng, Kuo, Yao-Jen, Wu, Jui-Jen, Su, Hsiu-Yun, Chu, Yuan-Hua, Wu, Wen-Ching, Yang, Tzu-Yi, Yamauchi, Hiroyuki
Format: Article
Language:English
Subjects:
Asymmetry
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!