Interfacial thermal stability and band alignment of Al2O3/HfO2/Al2O3/Si gate stacks grown by atomic layer deposition

• Published in: Journal of alloys and compounds 2014-04, Vol.591, p.240-246
• Main Authors: Wei, H.H., He, G., Chen, X.S., Cui, J.B., Zhang, M., Chen, H.S., Sun, Z.Q.
• Format: Article
• Language: English
• Subjects: Alloys; Aluminum oxide; Annealing; Annealing temperature; Band alignment; Condensed matter: electronic structure, electrical, magnetic, and optical properties; Deposition; Electron states and collective excitations in thin films, multilayers, quantum wells, mesoscopic and nanoscale systems; Electronic structure and electrical properties of surfaces, interfaces, thin films and low-dimensional structures; Exact sciences and technology; Gates; Hafnium oxide; High-k gate dielectrics; Physics; Silicon; Spectroscopy; Stacks; Thin films and multilayers; X-ray photoelectron
• ISSN: 0925-8388; 1873-4669
• DOI: 10.1016/j.jallcom.2013.12.152

•Al2O3/HfO2/Al2O3 gate stacks has been deposited on Si substrate by ALD.•Interface thermal stability related with annealing temperature has been studied.•Phase separation at 700°C and silicate formation at 900°C have been detected. Based on X-ray photoelectron spectroscopy (XPS) and oxygen energy loss spectra, influences of vacuum annealing temperature on the interfacial thermal stability and band alignment of Al2O3/HfO2/Al2O3/Si gate stacks deposited by atomic layer deposition has been investigated. It has been revealed that annealing the multilayered Al2O3/HfO2/Al2O3 structure from 500 to 600°C leads to the formation of the composited Hf–Al–O alloy thin film. Meanwhile, phase separation of Hf–Al–O into HfO2 and Al2O3 for samples annealed at 700°C and silicate formation for sample annealed at 900°C has been observed. The band profiles, obtained via oxygen energy loss spectroscopy, provided us some insight, which is both convenient and at the same time important, into the way to identify high-k dielectric materials, and we also found that Al2O3/HfO2/Al2O3/Si gate stacks annealing at suitable temperature range of 500–700°C could be a promising candidate for high-k gate dielectrics.