An On-Chip-Trainable Gaussian-Kernel Analog Support Vector Machine

An analog circuit architecture of Gaussian-kernel support vector machines having on-chip training capability has been developed. It has a scalable array processor configuration and the circuit size increases only in proportion to the number of learning samples. Thanks to the hardware-friendly algori...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2010-07, Vol.57 (7), p.1513-1524
Main Authors: Kyunghee Kang, Shibata, Tadashi
Format: Article
Language:English
Subjects:
Analog circuits
Analog VLSI
Chip formation
Chips
Circuits
Classification
CMOS technology
Gaussian circuit
Gaussian processes
Hardware
hardware-friendly algorithm
Joining processes
Learning
machine learning
Mathematical analysis
on-chip learning
Power dissipation
Semiconductor device measurement
Studies
subthreshold circuit
support vector machine
Support vector machine classification
Support vector machines
Testing
Training
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Description
Summary:An analog circuit architecture of Gaussian-kernel support vector machines having on-chip training capability has been developed. It has a scalable array processor configuration and the circuit size increases only in proportion to the number of learning samples. Thanks to the hardware-friendly algorithm employed in the present work, the learning function is realized by attaching a small additional circuitry to the SVM classifying hardware. The SVM classifying hardware is composed as an array of Gaussian circuits. Although the system is inherently analog, the input and output signals including training results are all available in digital format. Therefore, the learned parameters are easily stored and reused after training sessions. A proof-of concept chip containing 2-class, 2-D, 12-template classifier was designed and fabricated in a 0.18-μm CMOS technology. The experimental results obtained from the fabricated chips are presented and compared with theoretical calculation results. It can classify 8.7 x 10 5 vectors per second and the average power dissipation was 220 μW. The learning capability was tested using eight fabricated chips and the variability among these chips were evaluated. Successful operation of the chips was confirmed by measurement results, which demonstrates that on-chip-learning can compensate for analog imperfections.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2009.2034234