A Library-Based Early Soft Error Sensitivity Analysis Technique for SRAM-Based FPGA Design

• Published in: Journal of electronic testing 2013-08, Vol.29 (4), p.457-471
• Main Authors: Thibeault, C., Hariri, Y., Hasan, S. R., Hobeika, C., Savaria, Y., Audet, Y., Tazi, F. Z.
• Format: Article
• Language: English
• Subjects: Architecture; Avionics; CAE) and Design; Circuits and Systems; Computer-Aided Engineering (CAD; Construction; Design engineering; Electrical Engineering; Engineering; Error analysis; Failure analysis; Field programmable gate arrays; Mathematical analysis; Matlab; Product reliability; Sensitivity analysis; Soft errors
• ISSN: 0923-8174; 1573-0727
• DOI: 10.1007/s10836-013-5393-9

The goal of this work is to develop a methodical approach for analytical soft error sensitivity analysis in SRAM-based FPGAs. Compared to other non-destructive techniques, the proposed approach can be applied very early in a design flow. This is achieved by extracting information about an application under development from high level models (e.g. C/C++ descriptions or Matlab Simulink models) and then invoking pre-established libraries where other information related to soft error sensitivity of primitive components are stored beforehand. Our library-based approach is validated by comparing our early estimation results to those obtained through synthesis, placement and routing of complete designs, for two different ways of estimating the number of potentially critical configuration bits. We first explore two different design architectures for implementing Finite Impulse Response filters. The design architectures are explored under two different implementation options, for a Xilinx Virtex-5 FPGA: LUT based and DSP48E block based. Then we apply our estimation technique on a more complex design. namely a GMSK demodulator. Results show that the worst case relative error, caused by our estimation technique with respect to the results obtained after synthesis, placement and routing is 7,2 %, and in most cases, it is less than 5 %. Mean time between failures are provided for the different design architecture and implementation options, to illustrate how our technique can help designers make early choices to build more reliable designs without performing the whole implementation, as our early estimation results are close to those obtained later in the design process.