Towards high-performance packet processing on commodity multi-cores: current issues and future directions

The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. Howev...

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Bibliographic Details
Published in:Science China. Information sciences 2015-12, Vol.58 (12), p.1-16
Main Authors: Tang, Lu, Yan, JinLi, Sun, ZhiGang, Li, Tao, Zhang, MinXuan
Format: Article
Language:English
Subjects:
Buffers
Central processing units
Commodities
Computer Science
CPUs
Field programmable gate arrays
Information Systems and Communication Service
Microprocessors
Networks
Optimization
Packets (communication)
Research Paper
Test stands
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Summary:The demands of programmability have become more and more exigent as novel network services appear, such as E-commerce, social softwares, and online videos. Commodity multi-core CPUs have been widely applied in network packet processing to get high programmability and reduce the time-to-market. However, there is a great gap between the packet processing performance of commodity multi-core and that of the traditional packet processing hardware, e.g., NP (Network Process). Recently, optimization of the packet processing performance of commodity multi-cores has become a hot topic in industry and academia. In this paper, based on a detailed analysis of the packet processing procedure, firstly we identify two dominating overheads, namely the virtual-to-physical address translation and the packet buffer management. Secondly, we make a comprehensive survey on the current optimization methods. Thirdly, based on the survey, the heterogeneous architecture of the commodity multi-core + FPGA is proposed as a promising way to improve the packet processing performance. Fourthly, a novel Self-Described Buffer (SDB) management technology is introduced to eliminate the overheads of the allocation and deallocation of the packet buffers offloaded to FPGA. Then, an evaluation testbed, named PIOT (Packet I/O Testbed), is designed and implemented to evaluate the packet forwarding performance. I/O capacity of different commodity multi-core CPUs and the performance of optimization methods are assessed and compared based on PIOT. At last, the future work of packet processing optimization on multi-core CPUs is discussed.
ISSN:1674-733X
1869-1919
DOI:10.1007/s11432-015-5484-6