A CMOS Low-Dropout Regulator With Dominant-Pole Substitution

A dominant-pole substitution (DPS) technique for low-dropout regulator (LDO) is proposed in this paper. The DPS technique involves signal-current feedforward and amplification such that an ultralow-frequency zero is generated to cancel the dominant pole of LDO, while a higher frequency pole substitu...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on power electronics 2016-09, Vol.31 (9), p.6362-6371
Main Authors: Ho, Marco, Jianping Guo, Kai Ho Mak, Wang Ling Goh, Shi Bu, Yanqi Zheng, Xian Tang, Ka Nang Leung
Format: Article
Language:English
Subjects:
Bandwidth
Bandwidths
Capacitors
CMOS
Dominant pole
Electric currents
Electric potential
Electrical equipment
Electronic mail
Feedforward
low-dropout regulator (LDO)
Poles
Poles and zeros
Power supply
Regulators
Resistors
Response time
Transconductance
Transient analysis
Voltage
zero generation
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:A dominant-pole substitution (DPS) technique for low-dropout regulator (LDO) is proposed in this paper. The DPS technique involves signal-current feedforward and amplification such that an ultralow-frequency zero is generated to cancel the dominant pole of LDO, while a higher frequency pole substitutes in and becomes the new dominant pole. With DPS, the loop bandwidth of the proposed LDO can be significantly extended, while a standard value and large output capacitor for transient purpose can still be used. The resultant LDO benefits from both the fast response time due to the wide loop bandwidth and the large charge reservoir from the output capacitor to achieve the significant enhancement in the dynamic performances. Implemented with a commercial 0.18-μm CMOS technology, the proposed LDO with DPS is validated to be capable of delivering 100 mA at 1.0-V output from a 1.2-V supply, with current efficiency of 99.86%. Experimental results also show that the error voltage at the output undergoing 100 mA of load transient in 10-ns edge time is about 25 mV. Line transient responses reveal that no more than 20-mV instantaneous changes at the output when the supply voltage swings between 1.2 and 1.8 V in 100 ns. The power-supply rejection ratio at 3 MHz is -47 dB.
ISSN:0885-8993
1941-0107
DOI:10.1109/TPEL.2015.2503919