Diffusion and Gate Replacement: A New Gate-First High- k /Metal Gate CMOS Integration Scheme Suppressing Gate Height Asymmetry

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high-k, and then by rem...

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Bibliographic Details
Published in:IEEE transactions on electron devices 2016-01, Vol.63 (1), p.265-271
Main Authors: Ritzenthaler, Romain, Schram, Tom, Spessot, Alessio, Caillat, Christian, Moonju Cho, Simoen, Eddy, Aoulaiche, Marc, Albert, Johan, Soon-Aik Chew, Noh, Kyoung Bong, Yunik Son, Mitard, Jerome, Mocuta, Anda, Horiguchi, Naoto, Fazan, Pierre, Thean, Aaron Voon-Yew
Format: Article
Language:English
Subjects:
Aluminum oxide
Al₂O₃ capping layers
Annealing
Asymmetry
CMOS
CMOS integrated circuits
CMOS process integration
Compatibility
Devices
Diffusion
diffusion and gate replacement (D#x0026
GR)
dynamic random access memory (DRAM) periphery transistors
Gates
High K dielectric materials
high-k metal gate (HKMG)
La capping layers
Logic gates
Mg capping layers
MOS devices
MOSFET fabrication
Work functions
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Summary:In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high-k, and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al 2 O 3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al 2 O 3 ) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow.
ISSN:0018-9383
1557-9646
DOI:10.1109/TED.2015.2501721