Identification and Rejuvenation of NBTI-Critical Logic Paths in Nanoscale Circuits

The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults...

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Bibliographic Details
Published in:Journal of electronic testing 2016-06, Vol.32 (3), p.273-289
Main Authors: Jenihhin, Maksim, Squillero, Giovanni, Copetti, Thiago Santos, Tihhomirov, Valentin, Kostin, Sergei, Gaudesi, Marco, Vargas, Fabian, Raik, Jaan, Sonza Reorda, Matteo, Bolzani Poehls, Leticia, Ubar, Raimund, Medeiros, Guilherme Cardoso
Format: Article
Language:English
Subjects:
CAE) and Design
Circuits
Circuits and Systems
Computer-Aided Engineering (CAD
Delay
Electrical Engineering
Engineering
Logic
Nanostructure
Nanotechnology
Niobium base alloys
Semiconductor devices
Stimuli
Temperature
Transistors
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Summary:The Negative Bias Temperature Instability (NBTI) phenomenon is agreed to be one of the main reliability concerns in nanoscale circuits. It increases the threshold voltage of pMOS transistors, thus, slows down signal propagation along logic paths between flip-flops. NBTI may cause intermittent faults and, ultimately, the circuit’s permanent functional failures. In this paper, we propose an innovative NBTI mitigation approach by rejuvenating the nanoscale logic along NBTI-critical paths. The method is based on hierarchical identification of NBTI-critical paths and the generation of rejuvenation stimuli using an Evolutionary Algorithm. A new, fast, yet accurate model for computation of NBTI-induced delays at gate-level is developed. This model is based on intensive SPICE simulations of individual gates. The generated rejuvenation stimuli are used to drive those pMOS transistors to the recovery phase, which are the most critical for the NBTI-induced path delay. It is intended to apply the rejuvenation procedure to the circuit, as an execution overhead, periodically. Experimental results performed on a set of designs demonstrate reduction of NBTI-induced delays by up to two times with an execution overhead of 0.1 % or less. The proposed approach is aimed at extending the reliable lifetime of nanoelectronics.
ISSN:0923-8174
1573-0727
DOI:10.1007/s10836-016-5589-x