Coarse-grained reconfigurable hardware accelerator of machine learning classifiers

In this paper a universal, coarse-grained reconfigurable architecture for hardware acceleration of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs) is proposed. Using proposed architecture, two versions of DTs (Functional DT and Axis-Parallel DT), two versi...

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Bibliographic Details
Main Authors: Vranjkovic, Vuk, Struharik, Rastislav
Format: Conference Proceeding
Language:English
Subjects:
Acceleration
Artificial neural networks
Computer architecture
Computer programs
Data Mining
Data processing
Decision Trees
Electronics
Field programmable gate arrays
FPGA
Hardware
Hardware Acceleration
Machine Learning
R project
Random access memory
Reconfigurable Hardware
Software
Support vector machines
WEKA
Online Access:Get full text
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Summary:In this paper a universal, coarse-grained reconfigurable architecture for hardware acceleration of decision trees (DTs), artificial neural networks (ANNs), and support vector machines (SVMs) is proposed. Using proposed architecture, two versions of DTs (Functional DT and Axis-Parallel DT), two versions of SVMs (with polynomial and radial kernels) and two versions of ANNs (Multi Layer Perceptron and Radial Basis), have been implemented in FPGA. Experimental results, based on 18 benchmark datasets from standard UCI Machine Learning Repository Database, indicate that FPGA implementation provides significant improvement (1-3 orders of magnitude) in the average instance classification time, in comparison with software implementations, based on WEKA and R project.
ISSN:2157-8702
DOI:10.1109/IWSSIP.2016.7502737