SOMprocessor: A high throughput FPGA-based architecture for implementing Self-Organizing Maps and its application to video processing

• Published in: Neural networks 2020-05, Vol.125, p.349-362
• Main Authors: Sousa, Miguel Angelo de Abreu de, Pires, Ricardo, Del-Moral-Hernandez, Emilio
• Format: Article
• Language: English
• Subjects: FPGA; Neuromorphic chip; Self-organizing Maps; Unsupervised learning; Video surveillance
• ISSN: 0893-6080; 1879-2782
• DOI: 10.1016/j.neunet.2020.02.019

The design of neuromorphic chips aims to develop electronic circuits dedicated to executing artificial neural networks, mainly by exploring parallel processing. Unsupervised learning models, such as Self-organizing Maps (SOM), may benefit from massively concurrent hardware-based implementations to meet the requirements of real-time and embedded applications. This work first presents a theoretical analysis of the algorithms implemented in hardware to compute SOM learning and recall phases. This is important because, albeit similar, the processing steps executed in hardware are not necessarily identical to those executed in software. Then, the proposed FPGA architecture entitled SOMprocessor is shown in detail. The circuit of the processor explores two different computational strategies for increasing the performance of current state-of-the-art works. These computational strategies aim to improve the data flow through the processor and its flexibility to implement different network topologies. Finally, this work presents the application of the SOMprocessor to a video categorization task. The results show that topographic and quantization errors are similar between hardware and software implementations, as well as the overall accuracy. Moreover, the proposed FPGA architecture achieves acceleration of 3 to 4 orders of magnitude as compared to CPU executions.