Architecture of a digital signal processor

• Published in: IBM journal of research and development 1985-03, Vol.29 (2), p.132-139
• Main Authors: UNGERBOECK, G, MAIWALD, D, KAESER, H.-P, CHEVILLAT, P. R, BERAUD, J. P
• Format: Article
• Language: English
• Subjects: Applied sciences; Computers, microcomputers; Electronics; Exact sciences and technology; Hardware
• ISSN: 0018-8646; 2151-8556; 0018-8646
• DOI: 10.1147/rd.292.0132

A digital signal processor (DSP) is described which achieves high processing efficiency by executing concurrently four functions in every processor cycle: instruction prefetching from a dedicated instruction memory and generation of an effective operand, access to a single-port data memory and transfer of a data word over a common data bus, arithmetic/logic-unit (ALU) operation, and multiplication. Instructions have a single format and contain an operand, index control bits, and two independent operation codes called 'transfer' code and 'compute' code. The first code specifies the transfer of a data word over the common data bus, e.g., from data memory to a local register. The second determines an operation of the ALU on the contents of local registers. A fast free-running multiplier operates in parallel with the ALU and delivers a product in every cycle with a pipeline delay of two cycles. The architecture allows transversal-filter operations to be performed with one multiplication and ALU operation in every cycle. This is accomplished by a novel interleaving technique called ZIP-ing. The efficiency of the processor is demonstrated by programming examples.