Fault-tolerant neural network with concurrent error detection and correction capability

Although artificial neural networks (ANNs) are generally considered to be robust, faults in neural network hardware can result in output errors. In order for ANNs to be used in mission-critical areas, they will be required to have the capability of detecting and correcting fault-induced computation...

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Bibliographic Details
Published in:Canadian journal of electrical and computer engineering 1997-01, Vol.22 (1), p.13-18
Main Authors: Ekong, D. U., Wood, H. C., Abd-El-Barr, M. H.
Format: Article
Language:English
Subjects:
Built-in self-test
Computer architecture
Fault tolerance
Fault tolerant systems
Neurons
Program processors
Online Access:Get full text
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Summary:Although artificial neural networks (ANNs) are generally considered to be robust, faults in neural network hardware can result in output errors. In order for ANNs to be used in mission-critical areas, they will be required to have the capability of detecting and correcting fault-induced computation errors. In this paper, a fault-tolerant neural network architecture with concurrent error detection and correction capability is proposed. The output of each hidden- and output-layer neuron of the proposed architecture is computed by three different processors or processing elements (PEs), and the computation results are compared. Each PE is also self-testing, and this ensures that if there are similar errors in a majority of the compared PE results, these errors will be detected. The proposed fault-tolerant architecture has been compared with existing fault-tolerant architectures, and simulation results are presented which show that ANNs implemented with the proposed architecture are more reliable and have better fault tolerance.
ISSN:0840-8688
DOI:10.1109/CJECE.1997.7102016