Channel engineering for analog device design in deep submicron CMOS technology for system on chip applications

• Published in: IEEE transactions on electron devices 2002-09, Vol.49 (9), p.1558-1565
• Main Authors: Deshpande, H.V., Baohong Cheng, Woo, J.C.S.
• Format: Article
• Language: English
• Subjects: Channels; CMOS; CMOS integrated circuits; Design engineering; Devices; Digital; Integrated circuit design; Integrated circuit fabrication; Mixed analog-digital integrated circuits; Oxides; Performance enhancement; System on chip; Very-large-scale integration
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2002.801435

Scaling of analog CMOS in the deep submicron regime is challenging, particularly for mixed mode system on chip applications due to the tradeoff in design requirements for analog and digital applications. The conventional approach employing aggressive gate oxide and S/D junction scaling to suppress the two-dimensional (2-D) electrostatic coupling and related short channel effects that degrade the device behavior in the deep submicron regime, though, improves the digital performance. However, this approach is not sufficient to obtain a reasonable analog performance. This paper presents a comprehensive study on the analog performance of scaled MOSFETs and explores alternative ways for improving the analog performance of these devices. It is shown that an easily integrable innovative channel engineering scheme in the form of single pocket structures can be used in the standard logic CMOS process to significantly improve the device analog performance of the deep submicron devices.