Thoughts on core integration and test

• Main Author: Anderson, T.L.
• Format: Conference Proceeding
• Language: English
• Subjects: Application specific integrated circuits; Chip scale packaging; Logic design; Microprocessors; Production; Protocols; Semiconductor device testing; Semiconductor devices; Sockets; Standards organizations
• ISSN: 1089-3539; 2378-2250
• DOI: 10.1109/TEST.1997.639728

A number of initiatives have begun to address the integration and test of core-based chip design. Several organizations, including an IEEE Test Technology Technical Committee (TTTC) and working groups of the Virtual Socket Interface Alliance (VSIA), meet regularly to consider standards and solutions. The most immediate issue that a chip designer must face is the integration of a core (or cores) into the chip. Three main approaches are popular. FIFO-based interfaces are quite common for VO interconnect cores; they have simple protocol rules and mate up well with DMA designs in the application logic. The core might instead mate to a microprocessor or I/O bus. For example, a multi-function chip can use an on-chip PCI bus to connect together multiple cores with PCI interfaces. The final common approach is a bus defined explicitly by an ASIC vendor or core provider to interconnect cores. For all three types of core interconnection, handling functional operation is only half of the solution. As with all semiconductor devices, a core-based chip must be well tested in production to become a viable product.