A 1.8-V digital-audio sigma-delta modulator in 0.8-μm CMOS

• Published in: IEEE journal of solid-state circuits 1997-06, Vol.32 (6), p.783-796
• Main Authors: Rabii, S., Wooley, B.A.
• Format: Article
• Language: English
• ISSN: 0018-9200
• DOI: 10.1109/4.585245

Oversampling techniques based on sigma-delta ( capital sigma Delta ) modulation offer numerous advantages for the realization of high-resolution analog-to-digital (A/D) converters in a implementation of a CMOS capital sigma Delta modulator for digital-audio A/D conversion that operates from a single 1.8-V power supply. A cascaded modulator that maintains a large full-scale input range while avoiding signal clipping at internal nodes is introduced. The experimental modulator has been designed with fully differential switched-capacitor integrators employing different input and output common-mode levels and boosted clock drivers in order to facilitate low voltage operation. Precise control of common-mode levels, high power supply noise rejection, and low power dissipation are obtained through the use of two-stage, class A/AB operational amplifiers. At a sampling rate of 4 MHz and an oversampling ratio of 80, an implementation of the modulator in a 0.8- mu m CMOS technology with metal-to-polycide capacitors and NMOS and PMOS threshold voltages of +0.65 V and -0.75 V, respectively, achieves a dynamic range of 99 dB at a Nyquist conversion rate of 50 kHz. The modulator can operate from supply voltages ranging from 1.5-2.5 V, occupies an active area of 1.5 mm super(2), and dissipates 2.5 mW from a 1.8-V supply.