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A quaternary partial-response class-IV transceiver for 125 Mbit/s data transmission over unshielded twisted-pair cables: principles of operation and VLSI realization
The paper describes an experimental transceiver for full-duplex transmission at a rate of 125 Mbit/s over unshielded twisted-pair cables of ordinary voice-grade quality, intended for use in a fiber distributed data interface (FDDI) network. Quaternary partial-response class-IV (QPRIV) overall-channe...
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Published in: | IEEE journal on selected areas in communications 1995-12, Vol.13 (9), p.1656-1669, Article 1656 |
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Main Authors: | , , |
Format: | Article |
Language: | English |
Citations: | Items that this one cites Items that cite this one |
Online Access: | Get full text |
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Summary: | The paper describes an experimental transceiver for full-duplex transmission at a rate of 125 Mbit/s over unshielded twisted-pair cables of ordinary voice-grade quality, intended for use in a fiber distributed data interface (FDDI) network. Quaternary partial-response class-IV (QPRIV) overall-channel signaling with near-end crosstalk (NEXT) cancellation and maximum-likelihood sequence detection is employed. The spectral shape of the QPRIV signals facilitates equalization and achieving compliance with EMC regulations. Since in an FDDI system each transmitter can be clocked independently, the receiver must cope with phase drift between NEXT signals to be cancelled and signals received from the remote transmitter. With the chosen transceiver architecture, digital-to-analog conversion of transmit signals, analog-to-digital conversion of receive signals, and adaptive NEXT cancellation are performed synchronously with the transmitter clock. The rate change from transmit timing to controlled receive timing is accomplished by an adaptive equalizer in conjunction with an elastic buffer and occasional coefficient shifts. The equalizer is adjusted rapidly enough to allow for a maximal phase drift of +/-100 ppm. The implementation of all digital signal-processing functions in a single 0.5 mum CMOS VLSI prototype chip is discussed. The employed standard-cell design resulted in a power consumption of 6 W. Significantly lower power consumption can be achieved by custom design of highly repetitive processing elements |
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ISSN: | 0733-8716 1558-0008 |
DOI: | 10.1109/49.475538 |