Scalable shared-buffering ATM switch with a versatile searchable queue

• Published in: IEEE journal on selected areas in communications 1997-06, Vol.15 (5), p.773-784
• Main Authors: Yamanaka, H., Saito, H., Kondoh, H., Sasaki, Y., Yamada, H., Tsuzuki, M., Nishio, S., Notani, H., Iwabu, A., Ishiwaki, M., Kohama, S., Matsuda, Y., Oshima, K.
• Format: Article
• Language: English
• Subjects: Asynchronous transfer mode; CMOS technology; Communication switching; Large scale integration; Memory management; Research and development; Size control; Switches; Switching circuits; Switching systems
• ISSN: 0733-8716; 1558-0008
• DOI: 10.1109/49.594840

The shared-buffering architecture is promising to make a large-scale ATM switch with small buffer size. However, there are two important problems, namely, memory-access speed and complex-control implementation. Advanced 0.5 /spl mu/m CMOS technology now makes it possible to integrate a huge amount of memory, and enables us to apply more sophisticated architecture than ever before. We propose the funnel-structured expandable architecture with shared multibuffering and the advanced searchable-address queueing scheme for these two problems. The funnel structure gives a flexible capability to build various sizes of ATM switches which are proportional to the number of LSI chips. The searchable-address queue, in which all the addresses of the stored cells for different output ports are queued in a single-FIFO hardware and the earliest address is found by the search function provided inside the queue, can reduce the total memory capacity drastically, and enables the address queue to be contained inside the LSI chip. This technique also has a great advantage for implementing the multicast and multilevel priority-control functions. A 622 Mbit/s 32/spl times/8 ATM switch LSI chip set, which consists of a BX-LSI and a CX-LSI, is developed using 0.5 /spl mu/m pure CMOS technology. By using four chip sets, a 622 Mbit/s 32/spl times/32 switch can be installed on one board.