VLSI logic and fault simulation on general-purpose parallel computers

The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simula...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 1993-03, Vol.12 (3), p.446-460
Main Authors: Mueller-Thuns, R.B., Saab, D.G., Damiano, R.F., Abraham, J.A.
Format: Article
Language:English
Subjects:
Applied sciences
Circuit faults
Circuit simulation
Computational modeling
Computer simulation
Concurrent computing
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hardware
Integrated circuits
Logic
Message passing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Switches
Very large scale integration
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
cited_by cdi_FETCH-LOGICAL-c306t-ee2df707cd974fbb1e1896f812c7873b1450e8c43e5b160640e0a605be6bd3d63
cites cdi_FETCH-LOGICAL-c306t-ee2df707cd974fbb1e1896f812c7873b1450e8c43e5b160640e0a605be6bd3d63
container_end_page 460
container_issue 3
container_start_page 446
container_title IEEE transactions on computer-aided design of integrated circuits and systems
container_volume 12
creator Mueller-Thuns, R.B.
Saab, D.G.
Damiano, R.F.
Abraham, J.A.
description The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. Algorithms for parallel logic and fault simulation of synchronous gate-level designs are introduced. The algorithms are based on a partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message-passing and shared-memory machines.< >
doi_str_mv 10.1109/43.215006
format article
fullrecord <record><control><sourceid>proquest_cross</sourceid><recordid>TN_cdi_proquest_miscellaneous_28719112</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><ieee_id>215006</ieee_id><sourcerecordid>28719112</sourcerecordid><originalsourceid>FETCH-LOGICAL-c306t-ee2df707cd974fbb1e1896f812c7873b1450e8c43e5b160640e0a605be6bd3d63</originalsourceid><addsrcrecordid>eNo9kE1LxDAQhoMouK4evHrqQQQPXWeaNEmPsqy6sODBj2tJ0-lSST9M2oP_fitdFgaGYZ55GF7GbhFWiJA9Cb5KMAWQZ2yBGVexwBTP2QISpWMABZfsKoQfABRpki3Y5nv3sY1ct69tZNoyqszohijUzejMUHdtNNWeWvLGxf3o-y5Q1JtpcuQi2zX9OJAP1-yiMi7QzbEv2dfL5nP9Fu_eX7fr511sOcghJkrKSoGyZaZEVRRIqDNZaUys0ooX009A2gpOaYESpAACIyEtSBYlLyVfsofZ2_vud6Qw5E0dLDlnWurGkCdaYYaYTODjDFrfheCpyntfN8b_5Qj5f1C54Pkc1MTeH6UmWOMqb1pbh9OBUDrTgk_Y3YzVRHTaHh0HJR1vKQ</addsrcrecordid><sourcetype>Aggregation Database</sourcetype><iscdi>true</iscdi><recordtype>article</recordtype><pqid>28719112</pqid></control><display><type>article</type><title>VLSI logic and fault simulation on general-purpose parallel computers</title><source>IEEE Electronic Library (IEL) Journals</source><creator>Mueller-Thuns, R.B. ; Saab, D.G. ; Damiano, R.F. ; Abraham, J.A.</creator><creatorcontrib>Mueller-Thuns, R.B. ; Saab, D.G. ; Damiano, R.F. ; Abraham, J.A.</creatorcontrib><description>The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. Algorithms for parallel logic and fault simulation of synchronous gate-level designs are introduced. The algorithms are based on a partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message-passing and shared-memory machines.&lt; &gt;</description><identifier>ISSN: 0278-0070</identifier><identifier>EISSN: 1937-4151</identifier><identifier>DOI: 10.1109/43.215006</identifier><identifier>CODEN: ITCSDI</identifier><language>eng</language><publisher>New York, NY: IEEE</publisher><subject>Applied sciences ; Circuit faults ; Circuit simulation ; Computational modeling ; Computer simulation ; Concurrent computing ; Design. Technologies. Operation analysis. Testing ; Electronics ; Exact sciences and technology ; Hardware ; Integrated circuits ; Logic ; Message passing ; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices ; Switches ; Very large scale integration</subject><ispartof>IEEE transactions on computer-aided design of integrated circuits and systems, 1993-03, Vol.12 (3), p.446-460</ispartof><rights>1993 INIST-CNRS</rights><lds50>peer_reviewed</lds50><woscitedreferencessubscribed>false</woscitedreferencessubscribed><citedby>FETCH-LOGICAL-c306t-ee2df707cd974fbb1e1896f812c7873b1450e8c43e5b160640e0a605be6bd3d63</citedby><cites>FETCH-LOGICAL-c306t-ee2df707cd974fbb1e1896f812c7873b1450e8c43e5b160640e0a605be6bd3d63</cites></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://ieeexplore.ieee.org/document/215006$$EHTML$$P50$$Gieee$$H</linktohtml><link.rule.ids>314,776,780,27903,27904,54774</link.rule.ids><backlink>$$Uhttp://pascal-francis.inist.fr/vibad/index.php?action=getRecordDetail&amp;idt=4789843$$DView record in Pascal Francis$$Hfree_for_read</backlink></links><search><creatorcontrib>Mueller-Thuns, R.B.</creatorcontrib><creatorcontrib>Saab, D.G.</creatorcontrib><creatorcontrib>Damiano, R.F.</creatorcontrib><creatorcontrib>Abraham, J.A.</creatorcontrib><title>VLSI logic and fault simulation on general-purpose parallel computers</title><title>IEEE transactions on computer-aided design of integrated circuits and systems</title><addtitle>TCAD</addtitle><description>The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. Algorithms for parallel logic and fault simulation of synchronous gate-level designs are introduced. The algorithms are based on a partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message-passing and shared-memory machines.&lt; &gt;</description><subject>Applied sciences</subject><subject>Circuit faults</subject><subject>Circuit simulation</subject><subject>Computational modeling</subject><subject>Computer simulation</subject><subject>Concurrent computing</subject><subject>Design. Technologies. Operation analysis. Testing</subject><subject>Electronics</subject><subject>Exact sciences and technology</subject><subject>Hardware</subject><subject>Integrated circuits</subject><subject>Logic</subject><subject>Message passing</subject><subject>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</subject><subject>Switches</subject><subject>Very large scale integration</subject><issn>0278-0070</issn><issn>1937-4151</issn><fulltext>true</fulltext><rsrctype>article</rsrctype><creationdate>1993</creationdate><recordtype>article</recordtype><recordid>eNo9kE1LxDAQhoMouK4evHrqQQQPXWeaNEmPsqy6sODBj2tJ0-lSST9M2oP_fitdFgaGYZ55GF7GbhFWiJA9Cb5KMAWQZ2yBGVexwBTP2QISpWMABZfsKoQfABRpki3Y5nv3sY1ct69tZNoyqszohijUzejMUHdtNNWeWvLGxf3o-y5Q1JtpcuQi2zX9OJAP1-yiMi7QzbEv2dfL5nP9Fu_eX7fr511sOcghJkrKSoGyZaZEVRRIqDNZaUys0ooX009A2gpOaYESpAACIyEtSBYlLyVfsofZ2_vud6Qw5E0dLDlnWurGkCdaYYaYTODjDFrfheCpyntfN8b_5Qj5f1C54Pkc1MTeH6UmWOMqb1pbh9OBUDrTgk_Y3YzVRHTaHh0HJR1vKQ</recordid><startdate>19930301</startdate><enddate>19930301</enddate><creator>Mueller-Thuns, R.B.</creator><creator>Saab, D.G.</creator><creator>Damiano, R.F.</creator><creator>Abraham, J.A.</creator><general>IEEE</general><general>Institute of Electrical and Electronics Engineers</general><scope>IQODW</scope><scope>AAYXX</scope><scope>CITATION</scope><scope>7SC</scope><scope>7SP</scope><scope>7TB</scope><scope>8FD</scope><scope>FR3</scope><scope>JQ2</scope><scope>L7M</scope><scope>L~C</scope><scope>L~D</scope></search><sort><creationdate>19930301</creationdate><title>VLSI logic and fault simulation on general-purpose parallel computers</title><author>Mueller-Thuns, R.B. ; Saab, D.G. ; Damiano, R.F. ; Abraham, J.A.</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-LOGICAL-c306t-ee2df707cd974fbb1e1896f812c7873b1450e8c43e5b160640e0a605be6bd3d63</frbrgroupid><rsrctype>articles</rsrctype><prefilter>articles</prefilter><language>eng</language><creationdate>1993</creationdate><topic>Applied sciences</topic><topic>Circuit faults</topic><topic>Circuit simulation</topic><topic>Computational modeling</topic><topic>Computer simulation</topic><topic>Concurrent computing</topic><topic>Design. Technologies. Operation analysis. Testing</topic><topic>Electronics</topic><topic>Exact sciences and technology</topic><topic>Hardware</topic><topic>Integrated circuits</topic><topic>Logic</topic><topic>Message passing</topic><topic>Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices</topic><topic>Switches</topic><topic>Very large scale integration</topic><toplevel>peer_reviewed</toplevel><toplevel>online_resources</toplevel><creatorcontrib>Mueller-Thuns, R.B.</creatorcontrib><creatorcontrib>Saab, D.G.</creatorcontrib><creatorcontrib>Damiano, R.F.</creatorcontrib><creatorcontrib>Abraham, J.A.</creatorcontrib><collection>Pascal-Francis</collection><collection>CrossRef</collection><collection>Computer and Information Systems Abstracts</collection><collection>Electronics &amp; Communications Abstracts</collection><collection>Mechanical &amp; Transportation Engineering Abstracts</collection><collection>Technology Research Database</collection><collection>Engineering Research Database</collection><collection>ProQuest Computer Science Collection</collection><collection>Advanced Technologies Database with Aerospace</collection><collection>Computer and Information Systems Abstracts – Academic</collection><collection>Computer and Information Systems Abstracts Professional</collection><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext</fulltext></delivery><addata><au>Mueller-Thuns, R.B.</au><au>Saab, D.G.</au><au>Damiano, R.F.</au><au>Abraham, J.A.</au><format>journal</format><genre>article</genre><ristype>JOUR</ristype><atitle>VLSI logic and fault simulation on general-purpose parallel computers</atitle><jtitle>IEEE transactions on computer-aided design of integrated circuits and systems</jtitle><stitle>TCAD</stitle><date>1993-03-01</date><risdate>1993</risdate><volume>12</volume><issue>3</issue><spage>446</spage><epage>460</epage><pages>446-460</pages><issn>0278-0070</issn><eissn>1937-4151</eissn><coden>ITCSDI</coden><abstract>The authors define a general framework for the parallel simulation of digital systems and develop and evaluate tools for logic and fault simulation that have a good cost-performance ratio. They first review previous work and identify central issues. Then a high-level process model of parallel simulation is presented to clarify essential design choices. Algorithms for parallel logic and fault simulation of synchronous gate-level designs are introduced. The algorithms are based on a partitioning approach that reduces the number of necessary synchronizations between processors. A simple performance model characterizes the dependence on some crucial parameters. Experimental results for some large benchmarks are given, using prototype implementations for both message-passing and shared-memory machines.&lt; &gt;</abstract><cop>New York, NY</cop><pub>IEEE</pub><doi>10.1109/43.215006</doi><tpages>15</tpages></addata></record>
fulltext fulltext
identifier ISSN: 0278-0070
ispartof IEEE transactions on computer-aided design of integrated circuits and systems, 1993-03, Vol.12 (3), p.446-460
issn 0278-0070
1937-4151
language eng
recordid cdi_proquest_miscellaneous_28719112
source IEEE Electronic Library (IEL) Journals
subjects Applied sciences
Circuit faults
Circuit simulation
Computational modeling
Computer simulation
Concurrent computing
Design. Technologies. Operation analysis. Testing
Electronics
Exact sciences and technology
Hardware
Integrated circuits
Logic
Message passing
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Switches
Very large scale integration
title VLSI logic and fault simulation on general-purpose parallel computers
url http://sfxeu10.hosted.exlibrisgroup.com/loughborough?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-27T17%3A22%3A48IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-proquest_cross&rft_val_fmt=info:ofi/fmt:kev:mtx:journal&rft.genre=article&rft.atitle=VLSI%20logic%20and%20fault%20simulation%20on%20general-purpose%20parallel%20computers&rft.jtitle=IEEE%20transactions%20on%20computer-aided%20design%20of%20integrated%20circuits%20and%20systems&rft.au=Mueller-Thuns,%20R.B.&rft.date=1993-03-01&rft.volume=12&rft.issue=3&rft.spage=446&rft.epage=460&rft.pages=446-460&rft.issn=0278-0070&rft.eissn=1937-4151&rft.coden=ITCSDI&rft_id=info:doi/10.1109/43.215006&rft_dat=%3Cproquest_cross%3E28719112%3C/proquest_cross%3E%3Cgrp_id%3Ecdi_FETCH-LOGICAL-c306t-ee2df707cd974fbb1e1896f812c7873b1450e8c43e5b160640e0a605be6bd3d63%3C/grp_id%3E%3Coa%3E%3C/oa%3E%3Curl%3E%3C/url%3E&rft_id=info:oai/&rft_pqid=28719112&rft_id=info:pmid/&rft_ieee_id=215006&rfr_iscdi=true