Scalable processors in the billion-transistor era: IRAM

Members of the University of California, Berkeley, argue that the memory system will be the greatest inhibitor of performance gains in future architectures. Thus, they propose the intelligent RAM or IRAM. This approach greatly increases the on-chip memory capacity by using DRAM technology instead of...

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Bibliographic Details
Published in:Computer (Long Beach, Calif.) Calif.), 1997-09, Vol.30 (9), p.75-78
Main Authors: Kozyrakis, C.E., Perissakis, S., Patterson, D., Anderson, T., Asanovic, K., Cardwell, N., Fromm, R., Golbus, J., Gribstad, B., Keeton, K., Thomas, R., Treuhaft, N., Yelick, K.
Format: Article
Language:English
Subjects:
Bandwidth
Bridges
Computer architecture
Delay
Fabrication
Information technology
Microprocessor chips
Microprocessors
Out of order
Random access memory
Read-write memory
Semiconductors
Systems integration
Transistors
VLIW
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Summary:Members of the University of California, Berkeley, argue that the memory system will be the greatest inhibitor of performance gains in future architectures. Thus, they propose the intelligent RAM or IRAM. This approach greatly increases the on-chip memory capacity by using DRAM technology instead of much less dense SRAM memory cells. The resultant on-chip memory capacity coupled with the high bandwidths available on chip should allow cost-effective vector processors to reach performance levels much higher than those of traditional architectures. Although vector processors require explicit compilation, the authors claim that vector compilation technology is mature (having been used for decades in supercomputers), and furthermore, that future workloads will contain more heavily vectorizable components.
ISSN:0018-9162
1558-0814
DOI:10.1109/2.612252