Large‐Scale Vertically Interconnected Complementary Field‐Effect Transistors Based on Thermal Evaporation

• Published in: Small (Weinheim an der Bergstrasse, Germany) Germany), 2024-06, Vol.20 (24), p.e2309953-n/a
• Main Authors: Ran, Yuqia, Song, Yiwen, Jia, Xionghui, Gu, Pingfan, Cheng, Zhixuan, Zhu, Yunke, Wang, Qi, Pan, Yu, Li, Yanping, Gao, Yunan, Ye, Yu
• Format: Article
• Language: English
• Subjects: Bi2S3; Channels; complementary field‐effect transistors (CFETs); Evaporation; Field effect transistors; Integrated circuits; Interlayers; scalable electronics; thermal evaporation; Transistors; Voltage gain
• ISSN: 1613-6810; 1613-6829
• DOI: 10.1002/smll.202309953

With the rapid development of integrated circuits, there is an increasing need to boost transistor density. In addition to shrinking the device size to the atomic scale, vertically stacked interlayer interconnection technology is also an effective solution. However, realizing large‐scale vertically interconnected complementary field‐effect transistors (CFETs) has never been easy. Currently‐used semiconductor channel synthesis and doping technologies often suffer from complex fabrication processes, poor vertical integration, low device yield, and inability to large‐scale production. Here, a method to prepare large‐scale vertically interconnected CFETs based on a thermal evaporation process is reported. Thermally‐evaporated etching‐free Te and Bi2S3 serve as p‐type and n‐type semiconductor channels and exhibit FET on‐off ratios of 103 and 105, respectively. The vertically interconnected CFET inverter exhibits a clear switching behavior with a voltage gain of 17 at a 4 V supply voltage and a device yield of 100%. Based on the ability of thermal evaporation to prepare large‐scale uniform semiconductor channels on arbitrary surfaces, repeated upward manufacturing can realize multi‐level interlayer interconnection integrated circuits. A method to prepare large‐scale vertically interconnected CFETs based on a thermal evaporation process is reported. The thermally‐evaporated Te and Bi2S3 are chosen to serve as p‐type and n‐type semiconductor channels. The CFET inverter exhibits a clear switching behavior, indicating that thermal evaporation provides a powerful and reliable route to facilitate vertically stacked CMOS circuits.