Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model

An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this paper, which features 1) a conditional linear approximation method of the MAX/MIN timing operator, 2) an extended canonical representation of correlated timing variables, and 3) a variation pruning meth...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2006-06, Vol.25 (6), p.1183-1191
Main Authors: Lizheng Zhang, Chen, W., Hu, Y., Chen, C.C.
Format: Article
Language:English
Subjects:
Accuracy
Algorithm design and analysis
Algorithms
Analytical models
Approximation algorithms
Circuit performance analysis
Circuit simulation
Circuit testing
Circuits and systems
Computer simulation
Correlation
Design engineering
extended canonical timing model
Linear approximation
Mathematical analysis
Mathematical models
Nonlinear circuits
path reconvergence
process variation
statistical static timing analysis
Studies
System testing
Time measurements
Timing
very large scale integration (VLSI)
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Summary:An efficient and accurate statistical static timing analysis (SSTA) algorithm is reported in this paper, which features 1) a conditional linear approximation method of the MAX/MIN timing operator, 2) an extended canonical representation of correlated timing variables, and 3) a variation pruning method that facilitates intelligent tradeoff between simulation time and accuracy of simulation result. A special design focus of the proposed algorithm is on the propagation of the statistical correlation among timing variables through nonlinear circuit elements. The proposed algorithm distinguishes itself from existing block-based SSTA algorithms in that it not only deals with correlations due to dependence on global variation factors but also correlations due to signal propagation path reconvergence. Tested with the International Symposium on Circuits and Systems (ISCAS) benchmark suites, the proposed algorithm has demonstrated very satisfactory performance in terms of both accuracy and running time. Compared with Monte-Carlo-based statistical timing simulation, the output probability distribution got from the proposed algorithm is within 1.5% estimation error while a 350 times speed-up is achieved over a circuit with 5355 gates
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2005.855979