The quest of porous ELK materials for high performance logic technologies

• Published in: Microelectronic engineering 2006-11, Vol.83 (11), p.2055-2058
• Main Author: Hsia, Chin C.
• Format: Article
• Language: English
• Subjects: Applied sciences; Design. Technologies. Operation analysis. Testing; Effective Modulus (B); Electronics; Etch Stop Layer; Exact sciences and technology; Extreme low k; Integrated circuits; k Process; Microelectronic fabrication (materials and surfaces technology); Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Trench First Hard Mask Via First
• ISSN: 0167-9317; 1873-5568
• DOI: 10.1016/j.mee.2006.09.007

To meet the demand of lower interconnect delay, using lower dielectric constant material for BEOL is an inevitable choice for 65 nm and below high performance technology nodes. Porous low k material with k < 2.7 is required for this application. However, with its porous characteristics and inferior mechanical properties, maintaining a low post process effective dielectric constant ( k process) and meeting process and packaging reliability specifications are the major challenges to the successful integration of the material [M.S. Liang, in:Challenges in Cu/Low- K Integration, IEDM, 2004.]. Proper choice of the integration scheme [C.H. Yao et al., in: Porous ULK Process Technology Development for 65/45 nm Nodes, VMIC, 2005.] and careful adjustment of its associated individual processes are the first step for maintaining the k process and keeping the process away from latent damages to reliability. Trench First Hard Mask (TFHM) and Via First integration schemes were compared for the purpose [S.S. Lin et al., in: An Optimized Integration Scheme for 0.13 m Technology Node Dual-Damascene Cu Interconnect, IITC, 2000.]. In order to characterize the process window of the integration scheme, a systematical and statistical method (Structural Design Rule, SDR, calculation) is used with supplement of an innovative in-line e-beam inspection technique, Grey Level Measurement [M.D. Lei et al., in: In-line Semi-electrical Process Diagnosis Methodology for Integrated Process Window Optimization of 65 nm and below Technology Nodes, SPIE, 2006.] combined with a specially designed test pattern (Addressable Defect Array), which covers all densities/pitches/widths of vias/trenches. These methods and techniques help us to reach the optimal process window in a methodological and timely fashion. In addition, to overcome the inherent mechanical weakness of the porous low k material, extensive finite element modeling is used to design and define mechanically stronger structures for better die saw immunity and package robustness of various packaging requirements [T.C. Huang et al., Wire Bonding Failure Mechanisms and Simulations of Cu Low- K IMD Chip Packaging, AMC 2002.]. FEM technique is also used for the reliability robustness design and derivation of design rule constraints for meeting electro-migration and stress migration requirements. [T.C. Huang et al., in: Numerical Modeling and Characterization of the Stress Migration Behavior Upon Various 90 Nanometer Cu/Low k Interconnects