Monolayer Vacancy‐Induced MXene Memory for Write‐Verify‐Free Programming

• Published in: Small (Weinheim an der Bergstrasse, Germany) Germany), 2024-09, Vol.20 (36), p.e2402273-n/a
• Main Authors: Tan, Dongchen, Sun, Nan, Huang, Jijie, Zhang, Zhaorui, Zeng, Lijun, Li, Qikun, Bi, Sheng, Bu, Jingyuan, Peng, Yan, Guo, Qinlei, Jiang, Chengming
• Format: Article
• Language: English
• Subjects: Algorithms; Monolayers; MXene; MXenes; non‐gradual switch; non‐volatile memory; vacancy; write‐verify‐free
• ISSN: 1613-6810; 1613-6829; 1613-6829
• DOI: 10.1002/smll.202402273

The fundamental logic states of 1 and 0 in Complementary Metal‐Oxide‐Semiconductor (CMOS) are essential for modern high‐speed non‐volatile solid‐state memories. However, the accumulated storage signal in conventional physical components often leads to data distortion after multiple write operations. This necessitates a write‐verify operation to ensure proper values within the 0/1 threshold ranges. In this work, a non‐gradual switching memory with two distinct stable resistance levels is introduced, enabled by the asymmetric vertical structure of monolayer vacancy‐induced oxidized Ti3C2Tx MXene for efficient carrier trapping and releasing. This non‐cumulative resistance effect allows non‐volatile memories to attain valid 0/1 logic levels through direct reprogramming, eliminating the need for a write‐verify operation. The device exhibits superior performance characteristics, including short write/erase times (100 ns), a large switching ratio (≈3 × 104), long cyclic endurance (>104 cycles), extended retention (>4 × 106 s), and highly resistive stability (>104 continuous write operations). These findings present promising avenues for next‐generation resistive memories, offering faster programming speed, exceptional write performance, and streamlined algorithms. Non‐volatile memories based on vacancy‐induced oxidized monolayer Ti3C2Tx MXene demonstrate large switching ratio, high resistive stability, and endurance. Through a carrier trapping and releasing mechanism, the memory possesses a non‐accumulative resistive effect, enabling the memory to reach an effective 0/1 logic level by direct reprogramming without the need for a write verification operation.