Fast Cycle-accurate Behavioral Simulation for Pipelined Processors Using Early Pipeline Evaluation

Modeling and simulating pipelined processors in procedurallanguages such as C/C++ requires lots of cost in handlingconcurrent events, which hinders fast simulation. A number ofresearches on simulation have devised speed-up techniques toreduce the number of events. This paper presents a newsimulation...

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Bibliographic Details
Main Authors: Park, In-Cheol, Kang, Sehyeon, Yi, Yongseok
Format: Conference Proceeding
Language:English
Subjects:
Computer systems organization > Architectures > Serial architectures > Pipeline computing
Hardware > Hardware validation > Functional verification > Simulation and emulation
Software and its engineering > Software notations and tools > General programming languages > Language types
Online Access:Get full text
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Summary:Modeling and simulating pipelined processors in procedurallanguages such as C/C++ requires lots of cost in handlingconcurrent events, which hinders fast simulation. A number ofresearches on simulation have devised speed-up techniques toreduce the number of events. This paper presents a newsimulation approach developed to enhance the simulation ofpipelined processors. The proposed approach is based on earlypipeline evaluation that all the intermediate values of aninstruction are computed in advance, creating a future state for thenext instructions. The future state allows the next instructions tobe computed without considering data dependencies betweennearby instructions. We apply this concept to building a cycle-accurate simulator for a pipelined RISC processor and achieve almost the same speed as the instruction-level simulator.
ISSN:1092-3152
DOI:10.5555/996070.1009881