Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2^n)

This paper presents a reconfigurable curve-based cryptoprocessor that accelerates scalar multiplication of Elliptic Curve Cryptography (ECC) and HyperElliptic Curve Cryptography (HECC) of genus 2 over GF(2 n ). By allocating a copies of processing cores that embed reconfigurable Modular Arithmetic L...

Full description

Saved in:
Bibliographic Details
Published in:IEEE transactions on computers 2007-09, Vol.56 (9), p.1269-1282
Main Authors: Sakiyama, K., Batina, L., Preneel, B., Verbauwhede, I.
Format: Article
Language:English
Subjects:
Arithmetic
arithmetic and logic units
CMOS
Computer architecture
Cryptography
Elliptic curve cryptography
Hardware
Logic
Magnetic cores
Modular
Multiplication
Multiprocessor systems
Parallel processing
Polynomials
processor architectures
Public key cryptography
public key cryptosystems
reconfigurable hardware
Scalars
Citations: Items that this one cites
Items that cite this one
Online Access:Get full text
Tags: Add Tag
No Tags, Be the first to tag this record!
Description
Summary:This paper presents a reconfigurable curve-based cryptoprocessor that accelerates scalar multiplication of Elliptic Curve Cryptography (ECC) and HyperElliptic Curve Cryptography (HECC) of genus 2 over GF(2 n ). By allocating a copies of processing cores that embed reconfigurable Modular Arithmetic Logic Units (MALUs) over GF(2 n ), the scalar multiplication of ECC/HECC can be accelerated by exploiting Instruction-Level Parallelism (ILP). The supported field size can be arbitrary up to a(n + 1) - 1. The superscaling feature is facilitated by defining a single instruction that can be used for all field operations and point/divisor operations. In addition, the cryptoprocessor is fully programmable and it can handle various curve parameters and arbitrary irreducible polynomials. The cost, performance, and security trade-offs are thoroughly discussed for different hardware configurations and software programs. The synthesis results with a 0.13-mum CMOS technology show that the proposed reconfigurable cryptoprocessor runs at 292 MHz, whereas the field sizes can be supported up to 587 bits. The compact and fastest configuration of our design is also synthesized with a fixed field size and irreducible polynomial. The results show that the scalar multiplication of ECC over GF(2163) and HECC over GF(283) can be performed in 29 and 63 mus, respectively.
ISSN:0018-9340
1557-9956
DOI:10.1109/TC.2007.1071