Low-Power and Compact Sequential Circuits With Independent-Gate FinFETs

• Published in: IEEE transactions on electron devices 2008-01, Vol.55 (1), p.60-70
• Main Authors: Tawfik, S.A., Kursun, V.
• Format: Article
• Language: English
• Subjects: Brute force; Circuits; Clocks; contention current; Devices; double-gate MOSFET; Electric power generation; FinFET flip-flop; FinFET latch; FinFETs; Flip-flops; Gates (circuits); Latches; Logic gates; Monte Carlo; MOSFETs; multi-gate MOSFET; Power consumption; Sensors; Threshold voltage; Transistors
• ISSN: 0018-9383; 1557-9646
• DOI: 10.1109/TED.2007.911039

Scaling of the standard single-gate bulk MOSFETs faces great challenges in the nanometer regime due to the severe short-channel effects that cause an exponential increase in the leakage current and enhanced sensitivity to process variations. Multi-gate MOSFET technologies mitigate these limitations by providing a stronger control over a thin silicon body with multiple electrically coupled gates. Double-gate FinFET is the most attractive choice among the multi-gate transistor architectures because of the self-alignment of the two gates and the similarity of the fabrication steps to the existing standard CMOS technology. New latches and flip-flops based on independent-gate FinFETs are proposed in this paper to simultaneously reduce the power consumption and the circuit area. With the proposed independently biased double-gate FinFET sequential circuits, the active power consumption, the clock power, the leakage power, and the circuit area are reduced by up to 47%, 32%, 42%, and 20%, respectively, while maintaining similar speed and data stability as compared to the standard sequential circuits with tied-gate FinFETs in a 32-nm FinFET technology.