Models and Algorithmic Limits for an ECC-Based Approach to Hardening Sub-100-nm SRAMs

A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical c...

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Bibliographic Details
Published in:IEEE transactions on nuclear science 2007-08, Vol.54 (4), p.935-945
Main Authors: Bajura, M.A., Boulghassoul, Y.., Naseer, R.., DasGupta, S.., Witulski, A.F., Sondeen, J.., Stansberry, S.D., Draper, J.., Massengill, L.W., Damoulakis, J.N.
Format: Article
Language:English
Subjects:
Algorithms
Approximation
Bit error rate
Charge
Circuits
CMOS technology
Error correction codes
Error correction coding
Government
Hardening
Mathematical model
Mathematical models
memory fault tolerance
Power generation
Protection
radiation effects
Random access memory
Scrubbing
Space environment
Space technology
Static random access memory
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Summary:A mathematical bit error rate (BER) model for upsets in memories protected by error-correcting codes (ECCs) and scrubbing is derived. This model is compared with expected upset rates for sub-100-nm SRAM memories in space environments. Because sub-100-nm SRAM memory cells can be upset by a critical charge (Q crit ) of 1.1 fC or less, they may exhibit significantly higher upset rates than those reported in earlier technologies. Because of this, single-bit-correcting ECCs may become impractical due to memory scrubbing rate limitations. The overhead needed for protecting memories with a triple-bit-correcting ECC is examined relative to an approximate 2X ldquoprocess generationrdquo scaling penalty in area, speed, and power.
ISSN:0018-9499
1558-1578
DOI:10.1109/TNS.2007.892119