An Improved Switch Compensation Technique for Inverted R-2R Ladder DACs

Many recent applications are based on DSPs interfaced to analog I/0s with data converters. In this context, high-performance DACs have become crucial building blocks. The current-steering-flash DAC architecture is the most popular architecture for speed demanding applications. Although limited by co...

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Bibliographic Details
Published in:IEEE transactions on circuits and systems. I, Regular papers Regular papers, 2009-06, Vol.56 (6), p.1115-1124
Main Authors: Marche, D., Savaria, Y., Gagnon, Y.
Format: Article
Language:English
Subjects:
Architecture
Calibration
Circuit testing
Communication switching
Compensation
Data converters
Decoding
Design engineering
Design optimization
Devices
Digital signal processing
Digital-to-analog converter (DAC)
Electric circuits
Ladders
R-2R
Signal design
Signal to noise ratio
single-pole-double-throw (SPDT)
switch
Switches
Switching circuits
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Summary:Many recent applications are based on DSPs interfaced to analog I/0s with data converters. In this context, high-performance DACs have become crucial building blocks. The current-steering-flash DAC architecture is the most popular architecture for speed demanding applications. Although limited by component mismatches, resolution of these converters is typically enhanced by calibration solutions such as laser trimming or corrective active circuitry. Dynamic performances, on the other hand, are strongly dependent on switch design and operation which can easily spoil even the best static accuracy level at higher speeds. For this reason, much effort is concentrated on the design of clean switching processes to optimize signal to noise ratios delivered at the output of the DAC. In this paper, we present a novel switch sizing and compensation technique for inverted R-2R ladder DACs. While traditional switch compensation in the ladder leads to very large switch devices steering MSBs currents, our method allows current-steering with reduced equally sized switches. Results of 12-b DAC test chips fabricated in a 0.18 mum process show that this new technique allows significant area savings, without impairing static accuracy. Other improvements brought by this technique include simplified switch driving circuitry and improved settling time.
ISSN:1549-8328
1558-0806
DOI:10.1109/TCSI.2008.2008510