Modeling of Barrier-Engineered Charge-Trapping nand Flash Devices

Barrier-engineered charge-trapping NAND Flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multilayer barrier is derived using the Wentzel-Kramers-Brillouin approximation. The rigorously derived an...

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Bibliographic Details
Published in:IEEE transactions on device and materials reliability 2010-06, Vol.10 (2), p.222-232
Main Authors: Hang-Ting Lue, Sheng-Chih Lai, Tzu-Hsuan Hsu, Pei-Ying Du, Szu-Yu Wang, Kuang-Yeu Hsieh, Liu, Rich, Chih-Yuan Lu
Format: Magazinearticle
Language:English
Subjects:
Aluminum oxide
Approximation
barrier engineering (BE)
Barrier-engineered silicon-oxide-nitride-oxide-silicon (BE-SONOS)
Barriers
Beryllium
Buffer layers
Charge carrier processes
charge-trapping device
Devices
Dielectrics
Electron traps
Equations
Genetic programming
incremental-step pulse programming (ISPP)
Mathematical analysis
modeling
Multilayers
nand Flash
Nonhomogeneous media
Programming
SONOS devices
Tunneling
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Summary:Barrier-engineered charge-trapping NAND Flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multilayer barrier is derived using the Wentzel-Kramers-Brillouin approximation. The rigorously derived analytical form is valid for both electron and hole tunnelings, as well as for any barrier composition. With this, the time evolution (Vt-time) of any BE-CTNF device during programming/erasing can be accurately simulated. The model is validated by experimental results from bandgap-engineered silicon-oxide-nitride-oxide-silicon and various structures using an Al 2 O 3 top-capping layer. Using this model, various structures of BE-CTNF with high-κ tunneling or blocking dielectric are investigated. Finally, the impacts of barrier engineering on incremental-step pulse programming are examined.
ISSN:1530-4388
1558-2574
DOI:10.1109/TDMR.2010.2041665