Intrinsic doping and gate hysteresis in graphene field effect devices fabricated on SiO2 substrates

• Published in: Journal of physics. Condensed matter 2010-08, Vol.22 (33), p.334214-334214
• Main Authors: Joshi, P, Romero, H E, Neal, A T, Toutam, V K, Tadigadapa, S A
• Format: Article
• Language: English
• Subjects: Charge; Devices; Doping; Electric potential; Equipment Design; Equipment Failure Analysis; Gates; Graphene; Hysteresis; Materials Testing; Nanostructures - chemistry; Nanostructures - ultrastructure; Nanotechnology - instrumentation; Particle Size; Silicon dioxide; Silicon Dioxide - chemistry; Transistors, Electronic
• ISSN: 0953-8984; 1361-648X
• DOI: 10.1088/0953-8984/22/33/334214

We have studied the intrinsic doping level and gate hysteresis of graphene-based field effect transistors (FETs) fabricated over Si/SiO(2) substrates. It was found that the high p-doping level of graphene in some as-prepared devices can be reversed by vacuum degassing at room temperature or above depending on the degree of hydrophobicity and/or hydration of the underlying SiO(2) substrate. Charge neutrality point (CNP) hysteresis, consisting of the shift of the charge neutrality point (or Dirac peak) upon reversal of the gate voltage sweep direction, was also greatly reduced upon vacuum degassing. However, another type of hysteresis, consisting of the change in the transconductance upon reversal of the gate voltage sweep direction, persists even after long-term vacuum annealing at 200 °C, when SiO(2) surface-bound water is expected to be desorbed. We propose a mechanism for this transconductance hysteresis that involves water-related defects, formed during the hydration of the near-surface silanol groups in the bulk SiO(2), that can act as electron traps.