Mapping Statistical Process Variations Toward Circuit Performance Variability: An Analytical Modeling Approach

An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model. As verified with an industrial 90-nm technology, this analytical approach accurately predicts both nominal delay and delay variability over a wide range of power supply condit...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2007-10, Vol.26 (10), p.1866-1873
Main Authors: Yu Cao, Clark, L.T.
Format: Article
Language:English
Subjects:
Analytical models
Channel length
Channels
Circuit optimization
Circuits
CMOS technology
Delay
Delay effects
delay variability
Design engineering
Electricity supply industry
gate delay
Gates (circuits)
Mapping
Mathematical analysis
Mathematical models
Performance analysis
process variations
Propagation delay
Threshold voltage
Timing
Very large scale integration
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Summary:An analytical gate delay model is developed by integrating short-channel effects and the Alpha-power law-based timing model. As verified with an industrial 90-nm technology, this analytical approach accurately predicts both nominal delay and delay variability over a wide range of power supply conditions including subthreshold and strong- inversion regions. Excellent model scalability enables efficient mapping between process variations and delay variability at the gate level. Based on this model, the impact of various physical effects on delay variability has been identified. While the variation of effective channel length is the leading source for delay variability at the current 90-nm node, delay variability is actually more sensitive to the variation of threshold voltage, especially in the subthreshold region. Furthermore, the limitation of low-power design techniques is investigated in the presence of process variations, particularly dual V th and L biasing. These techniques become less effective at low V DD due to excessive delay variability.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2007.895613