Performance-Driven Crosstalk Elimination at Postcompiler Level-The Case of Low-Crosstalk Op-Code Assignment

• Published in: IEEE transactions on computer-aided design of integrated circuits and systems 2007-03, Vol.26 (3), p.564-573
• Main Authors: Wu-an Kuo, Yi-Ling Chiang, TingTing Hwang, Wu, A.C.-H.
• Format: Article
• Language: English
• Subjects: Algorithms; Capacitance; Codecs; Compiler; Compilers; Computer aided design; Crosstalk; Delay; Design engineering; Encoding; Energy consumption; high performance; instruction bus; Joining; Large scale integration; Logic; Power consumption; Propagation delay; Very large scale integration; Wire
• ISSN: 0278-0070; 1937-4151
• DOI: 10.1109/TCAD.2006.884861

Significant advances in very large-scale integration process technology have scaled the feature size down. One effect of this scaling down is that coupling capacitances have grown reciprocal in the square of the scaling factor. This crosstalk effect will not only increase the power consumption but also lengthen the propagation delay. Since the data sequences on an instruction bus are known during the compile time, this paper presents two compiler algorithms, rescheduling and renaming, for performance improvement by eliminating crosstalk effects on an instruction bus. The results show that our crosstalk-eliminating postcomplier algorithms significantly reduce the dynamic instruction overhead from 11.50% to 0.52% by eliminating the 4middotC crosstalk. Due to the effective 4middotC crosstalk elimination, our proposed method can improve the instruction fetch time up to 9.59%