Construction and Hardware-Efficient Decoding of Raptor Codes

• Published in: IEEE transactions on signal processing 2011-06, Vol.59 (6), p.2943-2960
• Main Authors: Zeineddine, Hady, Mansour, Mohammad M, Puri, Ranjit
• Format: Article
• Language: English
• Subjects: Algorithms; Applied sciences; Architecture; code construction; Codes; Coding, codes; Construction; Construction costs; decoder architecture; Decoders; Decoding; Detection, estimation, filtering, equalization, prediction; Encoding; Error correction; Exact sciences and technology; Hardware; Information, signal and communications theory; Iterative decoding; Joints; low-density parity-check codes; raptor codes; rate-less; Schedules; Signal and communications theory; Signal, noise; Telecommunications and information theory; Throughput
• ISSN: 1053-587X; 1941-0476
• DOI: 10.1109/TSP.2011.2114655

Raptor codes are a class of concatenated codes composed of a fixed-rate precode and a Luby-transform (LT) code that can be used as rateless error-correcting codes over communication channels. These codes have the atypical features of dynamic code-rate, highly irregular Tanner graph check-degree distribution, random LT-code structure, and LT-precode concatenation, which render a hardware-efficient decoder implementation achieving good error-correcting performance a challenging task. In this paper, the design of hardware-efficient Raptor decoders with good performance is addressed through joint optimizations targeting 1) the code construction, 2) decoding schedule, and 3) decoder architecture. First, random encoding is decoupled by developing a two-stage LT-code construction scheme that embeds structural features in the LT-graph that are amenable to efficient implementation while guaranteeing good performance. An LT-aware LDPC precode construction methodology that ensures architectural-compatibility with the structured LT code is also proposed. Second, a decoding schedule is optimized to reduce memory cost and account for processing workload-variability caused by the varying code rate. Third, to address the problems of check-degree irregularity and hardware underutilization, a novel reconfigurable check unit that attains a constant throughput while processing a varying number of LT and LDPC nodes is presented. These design steps collectively are employed to generate serial and partially-parallel decoder architectures. A Raptor code instance constructed using the proposed method having LT data-block length of 1210 is shown to outperform or closely match the performance of conventional LDPC codes over the code-rate range [0.4, 2 / 3 ]. The corresponding hardware serial decoder is synthesized using 65-nm CMOS technology and achieves a throughput of 22 Mb/s at rate 0.4 for a BER of 10 -6 , dissipates an average power of 222 mW at 1.2 V, and occupies an area of 1.77mm 2 .