Architecture and synthesis for on-chip multicycle communication

For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR micr...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2004-04, Vol.23 (4), p.550-564
Main Authors: Cong, J., Yiping Fan, Guoling Han, Xun Yang, Zhiru Zhang
Format: Article
Language:English
Subjects:
Architecture
Arrays
Clocks
Clustering algorithms
Communication system control
Computation
Computer science
Delay effects
Design engineering
Design methodology
Islands
Microarchitecture
Processor scheduling
Reduction
Registers
Synthesis
Wires
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Summary:For multigigahertz designs in nanometer technologies, data transfers on global interconnects take multiple clock cycles. In this paper, we propose a regular distributed register (RDR) microarchitecture, which offers high regularity and direct support of multicycle on-chip communication. The RDR microarchitecture divides the entire chip into an array of islands so that all local computation and communication within an island can be performed in a single clock cycle. Each island contains a cluster of computational elements, local registers, and a local controller. On top of the RDR microarchitecture, novel layout-driven architectural synthesis algorithms have been developed for multicycle communication, including scheduling-driven placement, placement-driven simultaneous scheduling with rebinding, and distributed control generation, etc. The experimentation on a number of real-life examples demonstrates promising results. For data flow intensive examples, we obtain a 44% improvement on average in terms of the clock period and a 37% improvement on average in terms of the final latency, over the traditional flow. For designs with control flow, our approach achieves a 28% clock-period reduction and a 23% latency reduction on average.
ISSN:0278-0070
1937-4151
DOI:10.1109/TCAD.2004.825872