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Modeling of interfacial sliding and film crawling in back-end structures of microelectronic devices

The fine-scale of interconnect structures in the back-end of modern microelectronic devices makes them susceptible to unusual, scale-sensitive deformation phenomena during processing or service because of internal stresses induced by thermal expansion mismatch between adjoining materials. During the...

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Bibliographic Details
Published in:IEEE transactions on components and packaging technologies 2005-09, Vol.28 (3), p.397-407
Main Authors: Dutta, I., Peterson, K.A., Park, C., Vella, J.
Format: Article
Language:English
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Summary:The fine-scale of interconnect structures in the back-end of modern microelectronic devices makes them susceptible to unusual, scale-sensitive deformation phenomena during processing or service because of internal stresses induced by thermal expansion mismatch between adjoining materials. During thermo-mechanical cycling associated with processing or service, dimensional changes may occur in Cu interconnect lines embedded in a low-K dielectric (LKD) due to plasticity/creep, strain incompatibilities may arise between Cu and LKD due to diffusionally accommodated interfacial sliding, and Cu lines may crawl or migrate via plastic deformation and interfacial sliding under far-field shear stresses imposed by the package. Although small, these effects can have a pronounced effect on component reliability. This paper presents shear-lag based modeling approaches to simulate out-of-plane (OOP) strain incompatibilities which arise within a single-layer Cu-LKD back-end structure (BES) during back-end processing, and in-plane (IP) deformation and migration of Cu interconnects within the BES after the chip is attached to a flip-chip package. Both models incorporate a previously developed constitutive interfacial sliding law, and help rationalize experimentally observed interfacial strain incompatibilities within Cu-LKD BES.
ISSN:1521-3331
1557-9972
DOI:10.1109/TCAPT.2005.853588