Utilizing the effect of relative delay on energy dissipation in low-power on-chip buses

This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A n...

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Bibliographic Details
Published in:IEEE transactions on very large scale integration (VLSI) systems 2004-12, Vol.12 (12), p.1348-1359
Main Authors: Ghoneima, M., Ismail, Y.I.
Format: Article
Language:English
Subjects:
Applied sciences
Buses
Buses (vehicles)
Capacitance
Circuits
CMOS
CMOS technology
Coupling capacitance
Delay
Delay effects
Delay lines
Design. Technologies. Operation analysis. Testing
Electronic equipment and fabrication. Passive components, printed wiring boards, connectics
Electronics
Encoding
Energy dissipation
Exact sciences and technology
Hardware
Integrated circuit technology
Integrated circuits
interconnect
low power
on-chip buses
Personal digital assistants
Power dissipation
Reduction
Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices
Switching
Throughput
Very large scale integration
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Summary:This paper presents an analysis of how the power dissipation of on-chip buses is affected by introducing a relative delay between the switching lines. Relative delay is shown to reduce the dissipated power of oppositely switching lines while causing a power penalty for similarly switching lines. A new low-power bus scheme that uses this effect is proposed and analyzed. As the introduced delay increases, the achieved power reduction increases while decreasing the bus throughput. Thus, a tradeoff between power reduction and throughput is required when selecting the imposed relative delay. The proposed low-power scheme, dynamic delayed line bus (DDL) scheme, led to a power reduction of up to 25%, 33%, and 42% when applied to data, address, and differential buses, respectively. Simple DDL hardware is designed and implemented in a 0.18-/spl mu/m TSMC CMOS technology and applied to a 4500-/spl mu/m long Metal4 bus. Circuit simulation results for different bus widths are presented.
ISSN:1063-8210
1557-9999
DOI:10.1109/TVLSI.2004.837993