Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems

• Published in: IEEE transactions on circuits and systems. 1, Fundamental theory and applications Fundamental theory and applications, 2005-07, Vol.52 (7), p.1348-1357
• Main Authors: Jaberipur, G., Parhami, B., Ghodsi, M.
• Format: Article
• Language: English
• Subjects: Arithmetic; Arithmetic unit; carry-free addition; Circuits; Compressors; computer arithmetic; Costs; digit set; Digital arithmetic; Digits; Encoding; Focusing; Hardware; hybrid redundancy; Integrated circuit interconnections; Leaves; number representation; Number systems; Redundant; redundant number system; Representations; signed-digit number system; stored-transfer representation; Studies; weighted bit-set (WBS) encoding
• ISSN: 1549-8328; 1057-7122; 1558-0806
• DOI: 10.1109/TCSI.2005.851679

We introduce the notion of two-valued digit (twit) as a binary variable that can assume one of two different integer values. Posibits, or simply bits, in {0,1} and negabits in {-1,0}, commonly used in two's-complement representations and (n,p) encoding of binary signed digits, are special cases of twits. A weighted bit-set (WBS) encoding, which generalizes the two's-complement encoding by allowing one or more posibits and/or negabits in each radix-2 position, has been shown to unify many efficient implementations of redundant number systems. A collection of equally weighted twits, including ones with noncontiguous values (e.g., {-1,1} or {0,2}), can lead to wider representation range without the added storage and interconnection costs associated with multivalued digit sets. We present weighted twit-set (WTS) encodings as a generalization of WBS encodings, examine key properties of this new class of encodings, and show that any redundant number system (e.g., generalized signed-digit and hybrid-redundant systems), including those that are based on noncontiguous and/or zero-excluded digit sets, is faithfully representable by WTS encoding. We highlight this broad coverage by a tree chart having WTS representations at its root and various useful redundant representations at its many internal nodes and leaves. We further examine how highly optimized conventional components such as standard full/half-adders and compressors may be used for arithmetic on WTS-encoded operands, thus allowing highly efficient and VLSI-friendly circuit implementations. For example, focusing on the WBS-like subclass of WTS encodings, we describe a twit-based implementation of a particular stored-transfer representation which offers area and speed advantages over other similar designs based on WBS and hybrid-redundant representations.