Hierarchical analysis of power distribution networks

Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The avai...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2002-02, Vol.21 (2), p.159-168
Main Authors: Zhao, M., Panda, R.V., Sapatnekar, S.S., Blaauw, D.
Format: Article
Language:English
Subjects:
AC generators
Admittance
Circuit simulation
Computation
Computer networks
Computing time
Design engineering
Integer linear programming
Integrated circuit interconnections
Linear programming
Mathematical models
Matrices
Microprocessors
Networks
Noise robustness
Power distribution
Power grids
Power systems
Run time (computers)
Studies
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Summary:Careful design and verification of the power distribution network of a chip are of critical importance to ensure its reliable performance. With the increasing number of transistors on a chip, the size of the power network has grown so large as to make the verification task very challenging. The available computational power and memory resources impose limitations on the size of networks that can be analyzed using currently known techniques. Many of today's designs have power networks that are too large to be analyzed in the traditional way as flat networks. In this paper, we propose a hierarchical analysis technique to overcome the aforesaid capacity limitation. We present a new technique for analyzing a power grid using macromodels that are created for a set of partitions of the grid. Efficient numerical techniques for the computation and sparsification of the port admittance matrices of the macromodels are presented. A novel sparsification technique using a 0-1 integer linear programming formulation is proposed to achieve superior sparsification for a specified error. The run-time and memory efficiency of the proposed method are illustrated on industrial designs. It is shown that even for a 60 million-node power grid, our approach allows for an efficient analysis, whereas previous approaches have been unable to handle power grids of such size.
ISSN:0278-0070
1937-4151
DOI:10.1109/43.980256