Floating-point behavioral synthesis

Traditionally, the data processed by a synthesized digital design is fixed (occasionally variable) width integer, and the functional units available are concomitantly simple ladders, subtractors, multipliers, multiplexers, and so on). The aims of paper work are two-fold: 1) to provide a library of h...

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Bibliographic Details
Published in:IEEE transactions on computer-aided design of integrated circuits and systems 2001-07, Vol.20 (7), p.828-839
Main Authors: Baidas, Z., Brown, A.D., Williams, A.C.
Format: Article
Language:English
Subjects:
Algorithms
Application specific integrated circuits
Computer science
Control system synthesis
Delay
Design engineering
Design optimization
Digital computers
Field programmable gate arrays
Floating point arithmetic
Hardware
Integrated circuit synthesis
Iterative algorithms
Libraries
Mathematical models
Optimization
Optimization algorithms
Optimization techniques
Quadratic equations
Software libraries
Studies
Synthesis
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Summary:Traditionally, the data processed by a synthesized digital design is fixed (occasionally variable) width integer, and the functional units available are concomitantly simple ladders, subtractors, multipliers, multiplexers, and so on). The aims of paper work are two-fold: 1) to provide a library of high-level floating-point functions (trigonometric, transcendental, complex) to support the synthesis of behavioral designs incorporating complicated sets of floating-point operations and 2) to incorporate this into an optimizing behavioral synthesis environment. Floating-point units are large and cumbersome and an optimization technique that allows the internal substructures of these units to be shared (in both space and time) produces a dramatic decrease in the overall hardware resources required to support a design. The floating-point modules themselves are each implemented in several ways: as an iterative series, by table lookup, and using the coordinate rotation digital computer algorithm. The choice of implementation is left to the optimizer, which makes individual binding choices based on global knowledge of the overall design. This paper describes the library and the optimization algorithm and demonstrates the overall system use with an exemplar: a floating-point quadratic equation solver capable of delivering complex roots, realized using 30% of a Xilinx 40125XV field-programmable gate array.
ISSN:0278-0070
1937-4151
DOI:10.1109/43.931000