STM patterned nanowire measurements using photolithographically defined implants in Si(100)

Using photolithographically defined implant wires for electrical connections, we demonstrate measurement of a scanning tunneling microscope (STM) patterned nanoscale electronic device on Si(100). By eliminating onerous alignment and complex lithography techniques, this approach is accessible to rese...

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Bibliographic Details
Published in:Scientific reports 2018-01, Vol.8 (1), p.1790-10, Article 1790
Main Authors: Ramanayaka, A. N., Kim, Hyun-Soo, Tang, Ke, Wang, X., Silver, R. M., Stewart, M. D., Pomeroy, J. M.
Format: Article
Language:English
Subjects:
142/126
639/301/357/1018
639/766/119/544
639/925/357/1016
639/925/927/481
639/925/930/2735
Aluminum
Humanities and Social Sciences
multidisciplinary
Nanotechnology
Phosphine
Photolithography
Science
Science (multidisciplinary)
Short term memory
Transplants & implants
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Summary:Using photolithographically defined implant wires for electrical connections, we demonstrate measurement of a scanning tunneling microscope (STM) patterned nanoscale electronic device on Si(100). By eliminating onerous alignment and complex lithography techniques, this approach is accessible to researchers in smaller efforts who may not have access to tools like electron beam lithography. Electrical contact to the nanodevices is achieved by implanting patterned, degenerately doped wires in the substrate using photolithography and commercial low energy ion implantation. We bring several isolated, implanted wires to within the STM scanner’s field of view where the STM can detect and smoothly draw contiguous patterns that directly overlap with implant lines for electrical connections. This overlapping provides a two-dimensional (2D) overlap interface with the 2D electron system, in contrast to many state-of-the-art methods that rely on contacting an exposed edge. After the STM pattern is phosphine dosed and overgrown with silicon, photolithography is then used again to align (≈ 160  μ m) 2 aluminum contact pads onto (≈ 200  μ m) 2 implanted areas at the ends of the wires. We present detailed results that optimize the spacing of neighboring wires while maintaining electrical isolation after heating to > 1200 °C, a step required for in situ Si surface preparation.
ISSN:2045-2322
2045-2322
DOI:10.1038/s41598-018-20042-8