Design and FPGA implementation machine learning based steller matrix encryption and decryption for high throughput and low latency

• Main Authors: Rajashekhar, U., Kumar, K. Pradeep, Kumara, M. Niranjana, Viswanath, K.
• Format: Conference Proceeding
• Language: English
• Subjects: Algorithms; Arithmetic; Audio data; Audio signals; Coders; Communications systems; Cryptography; Data encryption; Data transfer (computers); Data transmission; Delay; Encryption; Error reduction; Field programmable gate arrays; Flip-flops; Hardware; High speed; Integrated circuits; Iterative methods; Low cost; Machine learning; Model testing; Optimization; Power consumption; Prototypes; Security; Software
• ISSN: 0094-243X; 1551-7616
• DOI: 10.1063/5.0166105

As there are a lot of data thieves in the international media, numerous methods are there for keeping data secure. Visual communication, audio, public security, bandwidth, transmitter speed, and data-detecting equipment are the fundamental ideas of data transmission. The transmitted data can be protected in various ways; the Advanced Encryption Standard (AES) is used to protect sensitive knowledge in several sectors. The paper’s first section examines the need for and importance of communication system security for data encryption and decryption. The three Bit Encryption and Decryption Techniques (BEDT) schemes are proposed and evaluated with more examples to overcome the higher power consumption and complex operations in Add around the critical block of AES. The proposed BEDT systems are more efficient than current solutions. But AES is having significant issues with the number of steps in the calculation of Mix column iteration in the domain, so it has slowed down the operation, expanded the area of slices, and added delay. As a result, we propose the Stellar Matrix (SM) approach for the cryptographic algorithm as a novel strategy for the Mix column block set for Faster Processing System to perform both the encryption and decryption process. This SM-based cryptography is a good solution for optimizing an area in terms of the number of slices, the speed in terms of the processing time, the delay in nanoseconds, and the calculation in terms of the number of steps. After the research, the BEDT schemes and SM were combined into a single physical model to build a high-security, high-speed prototype hardware model. The developed model will be low-cost and high-speed, and its performance will be compatible with low resource use, such as memory, flip-flops, slices, and arithmetic operations, among other things. The final SM design is trained using ANN to minimize the error between the decoder and encoder input data in an iterative process. After training around 1000 iterations, an error has been reduced to 0.012. Finally, a novel cryptographic system with a high level of security, high data transfer speed, and encryption and decryption operations has been designed. The proposed method will reduce the hardware resources in real-time IC chips in software and hardware. The built model was tested with data from image, video, and audio signals, and the encryption and decryption operations were found to operate successfully. The prototype will be low-cost and high-spe