Design and implementation of high speed pipeline a/d converter for image processing and communication based applications

• Main Authors: Basavarajappa, Kiran, Rather, Nayeem Ahmed
• Format: Conference Proceeding
• Language: English
• Subjects: Analog circuits; Analog to digital converters; Design; Dynamic range; High speed; Image processing; Noise levels; Operational amplifiers; Power consumption; Transconductance
• ISSN: 0094-243X; 1551-7616
• DOI: 10.1063/5.0209199

Increasing the speed of an analog and mixed mode signal circuit without compromising power consumption is a difficulty in very large scale integrated (VLSI) design. This study work is carried out to construct a 12-bit Pipeline A/D converter (ADC) with 400MS/s sample rate to fulfil the high computational needs. In order to accommodate various applications, the design is concentrated on determining high speed and resolution in pipeline ADC. The pipeline method’s key benefits include ease of implementation, increased speed, and ease of layout design. A pipeline ADC architecture is designed using a proposed method that multiplies the D/A converter, comparator, sample and hold circuit (S/H), and operational transconductance amplifier (OTA). A switching capacitor integrator module is used by OTA to convert a differential input voltage into a current. The insertion of a S/H circuit in the pipeline ADC’s initial stage eliminates the need for a separate S/H amplifier. The obtained results indicate that the integral and differential non-linear values are, respectively, +0.61/-0.75LSB and +0.48/-0.55LSB. A value of 64.2 dB of Signal to Noise Dynamic Range (SNDR) and 81.8 dB of Spurious Free Dynamic Range (SFDR) is derived through simulation and plotted. The suggested design for the 45nm gpdk library is designed, simulated, and verified using an EDA platform with a cadence tool.