Parallel Error Detection for Leading Zero Anticipation

The algorithm and its implementation of the leading zero anticipation (LZA) are very vital for the performance of a high-speed floating-point adder in today’s state of art microprocessor design. Unfortunately, in predicting “shift amount” by a conventional LZA design, the result could be off by one...

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Bibliographic Details
Published in:Journal of computer science and technology 2006-11, Vol.21 (6), p.901-906
Main Authors: Zhang, Ge, Hu, Wei-Wu, Qi, Zi-Chu
Format: Article
Language:English
Subjects:
Algorithms
Circuits
Error detection
Floating point arithmetic
High speed
Microprocessors
Performance enhancement
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Summary:The algorithm and its implementation of the leading zero anticipation (LZA) are very vital for the performance of a high-speed floating-point adder in today’s state of art microprocessor design. Unfortunately, in predicting “shift amount” by a conventional LZA design, the result could be off by one position. This paper presents a novel parallel error detection algorithm for a general-case LZA. The proposed approach enables parallel execution of conventional LZA and its error detection, so that the error-indication signal can be generated earlier in the stage of normalization, thus reducing the critical path and improving overall performance. The circuit implementation of this algorithm also shows its advantages of area and power compared with other previous work.
ISSN:1000-9000
1860-4749
DOI:10.1007/s11390-006-0901-3