Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking

Geometric scaling of the conventional silicon MOSFET following Moore’s law down to the 14nm or even lower dimension technology node presents many fundamental challenges. Therefore, three-dimensional integrated circuit (3-D IC) architectures emerge as a game changer to the continuation of the Moore’s...

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Bibliographic Details
Main Authors: Zhiheng Huang, Paul Conway
Format: Default Conference proceeding
Published: 2014
Subjects:
Mechanical engineering not elsewhere classified
Reliability
Electronics
Interconnect
Mechanical Engineering not elsewhere classified
Online Access:https://hdl.handle.net/2134/17780
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https://hdl.handle.net/2134/17780

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