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Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking
Geometric scaling of the conventional silicon MOSFET following Moore’s law down to the 14nm or even lower dimension technology node presents many fundamental challenges. Therefore, three-dimensional integrated circuit (3-D IC) architectures emerge as a game changer to the continuation of the Moore’s...
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| Main Authors: | , |
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| Format: | Default Conference proceeding |
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2014
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| Online Access: | https://hdl.handle.net/2134/17780 |
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| _version_ | 1818172892374892544 |
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| author | Zhiheng Huang Paul Conway |
| author_facet | Zhiheng Huang Paul Conway |
| author_sort | Zhiheng Huang (6187427) |
| collection | Figshare |
| description | Geometric scaling of the conventional silicon MOSFET following Moore’s law down to the 14nm or even lower dimension technology node presents many fundamental challenges. Therefore, three-dimensional integrated circuit (3-D IC) architectures emerge as a game changer to the continuation of the Moore’s law. Staking multiple chips by the through-silicon-vias and microbumps has been proved to be a viable technology. However, 3-D ICs are facing challenges in design, materials and reliability issues. This paper introduces a microstructure-based multiphysics modeling platform that integrates multiscale microstructural evolution modeling, quantification of microstructural features, and modeling of microstructure-level responses of the 3-D interconnects under thermal, mechanical and electrical fields. Multiscale microstructures formed in the interconnects during processes of solidification, aging, and electromigration under effects from geometries and external stresses are presented first. Different methods such as singular value decomposition (SVD), wavelet multi-resolution analysis, and radon transformation are then used to quantification of the microstructural characteristics in 3-D interconnects. Based on the quantified microstructural index, an effort to establish a microstructure-interconnect performance relationship is introduced. Finally, the response of microstructure under multiphysics fields and its implications to design reliable 3-D interconnects are discussed. |
| format | Default Conference proceeding |
| id | rr-article-9548840 |
| institution | Loughborough University |
| publishDate | 2014 |
| record_format | Figshare |
| spelling | rr-article-95488402014-01-01T00:00:00Z Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking Zhiheng Huang (6187427) Paul Conway (1249635) Mechanical engineering not elsewhere classified Reliability Electronics Interconnect Mechanical Engineering not elsewhere classified Geometric scaling of the conventional silicon MOSFET following Moore’s law down to the 14nm or even lower dimension technology node presents many fundamental challenges. Therefore, three-dimensional integrated circuit (3-D IC) architectures emerge as a game changer to the continuation of the Moore’s law. Staking multiple chips by the through-silicon-vias and microbumps has been proved to be a viable technology. However, 3-D ICs are facing challenges in design, materials and reliability issues. This paper introduces a microstructure-based multiphysics modeling platform that integrates multiscale microstructural evolution modeling, quantification of microstructural features, and modeling of microstructure-level responses of the 3-D interconnects under thermal, mechanical and electrical fields. Multiscale microstructures formed in the interconnects during processes of solidification, aging, and electromigration under effects from geometries and external stresses are presented first. Different methods such as singular value decomposition (SVD), wavelet multi-resolution analysis, and radon transformation are then used to quantification of the microstructural characteristics in 3-D interconnects. Based on the quantified microstructural index, an effort to establish a microstructure-interconnect performance relationship is introduced. Finally, the response of microstructure under multiphysics fields and its implications to design reliable 3-D interconnects are discussed. 2014-01-01T00:00:00Z Text Conference contribution 2134/17780 https://figshare.com/articles/conference_contribution/Quantitative_characterisation_of_multi_scale_microstructures_in_interconnects_for_multi-chip_stacking/9548840 CC BY-NC-ND 4.0 |
| spellingShingle | Mechanical engineering not elsewhere classified Reliability Electronics Interconnect Mechanical Engineering not elsewhere classified Zhiheng Huang Paul Conway Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking |
| title | Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking |
| title_full | Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking |
| title_fullStr | Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking |
| title_full_unstemmed | Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking |
| title_short | Quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking |
| title_sort | quantitative characterisation of multi scale microstructures in interconnects for multi-chip stacking |
| topic | Mechanical engineering not elsewhere classified Reliability Electronics Interconnect Mechanical Engineering not elsewhere classified |
| url | https://hdl.handle.net/2134/17780 |